Silicon based integrated circuits are susceptible to electrostatic discharge (ESD) damage, particularly in the situation where a user of a device containing an integrated circuit develops a static charge on their body and subsequently comes in contact with the device containing the integrated circuit. The electrostatic charge induced in a human body may produce a voltage on the order of 5,000 volts. As most integrated circuits operate at no higher than five volts, an electrostatic discharge from a human body can be a traumatic experience for the integrated circuit. One way to provide an integrated circuit with ESD protection is to build an integrated circuit on a substrate that is less susceptible to damage from ESD. The integrated circuit may be fabricated on bulk silicon substrates, silicon on insulator (SOI) substrates, or separation by implantation of oxygen (SIMOX) substrates.
The thickness of the top silicon layer of SOI or SIMOX substrates wafers is on the order of 200 nm to 400 nm. If it is desired to fabricate a complimentary metal oxide semiconductor (CMOS) that becomes fully depleted, the conventional film is considerably thicker than is required. A fully depleted CMOS has advantages over a partially depleted CMOS, which advantages are generally referred to as less short channel effect, high speed and "no-kink" effect or a no-parasitic bipolar effect. Additionally, better control is possible over the fabrication process.
In the prior art, however, ESD protection has been minimal in case of fully depleted SIMOX devices. To manufacture a fully depleted SIMOX/SOI CMOS, the film must be thinned to no thicker than 50 nm, for sub-micron CMOS applications. The most suitable ESD protection device on this very thin silicon film is a p-n junction device. However, for diode protection, the junction area is determined by the thickness of the silicon film, and requires a very large area to form the diode.